The invention relates to a high speed complementary bipolar/CMOS process that provides a doping profile in the collectors of NPN transistors formed in an epitaxial layer so as to eliminate or reduce P-type auto doping and to avoid a "dip" in N type dopant concentration, which dip causes slow speed and other undesirable properties of the NPN transistors, and more specifically relates to further improvements of the high speed complementary/CMOS process to make it suitable for use in single-wafer reactors.
Those skilled in the art know that it is difficult to provide a process for manufacturing an epitaxial silicon layer that is satisfactory for use in a high speed complementary bipolar/CMOS process. In such a process a very thin, lightly doped N type epitaxial silicon layer must be grown on a silicon wafer including both pre-formed P+ boron doped buried layers and N+ arsenic doped buried layers formed in a P- substrate. In a typical prior art complementary bipolar/CMOS process the epitaxial layer is doped lightly in situ with arsenic to concentration of approximately 2.times.10.sup.15 cm.sup.-3 to achieve an optimal combination of characteristics of NPN, PNP and CMOS transistors to be formed. After the epitaxial deposition, the collector regions of the PNP and NPN transistors and the CMOS "wells" are further doped by a combination of low energy and high energy boron or phosphorous implants, with energies and doses tailored to the needs of various "families" of devices. During conventional epitaxial growth and subsequent conventional thermal processing, both the P type buried layers and the N type buried layers updiffuse into the epitaxial layer. That reduces the thickness of the useful portions of the collector regions for the transistors being fabricated. Since the P+ and N+ buried layers diffuse at significantly different rates, the PNP transistors end up having shallower collectors than the NPN transistor.
Since the diffusion of a P+ buried layer accelerates more rapidly than an N+ layer with respect to temperature, differences in the thicknesses of the collectors of the PNP transistors and the NPN transistors can be minimized by keeping the "Dt" of all high temperature process steps as low as possible. ("Dt" is a term referring to the cumulative amount of time and diffusivity that the wafer is subjected to high temperatures, usually exceeding 1000.degree. C., after the epitaxial layer has been deposited.) The deep double implants used to form the collectors of the required depth for the NPN and PNP transistors, respectively, eliminate the need for high Dt diffusions after the formation of the epitaxial layer.
Note that a drawback associated with the large differential dopant diffusivity of arsenic buried layers and boron buried layers remains even for "low Dt processing". For very low Dt processes, achieving the desirable PNP collector often results in producing an undesirable lightly doped N type subregion where an NPN collector region meets the N+ buried layer.
Furthermore, the value of N- dopant in the epitaxial layer must be selected to achieve the best characteristics of both the PNP and NPN transistors. If the N- concentration is as high as would be desirable for the NPN collector regions, then it would be far too high for the collectors of the PNP transistors. Therefore, a lower N- epitaxial dopant level, indicated by numeral 14 in FIG. 2, is selected instead. Then an N type ion implantation is applied to the surface, raising the N type dopant concentration to a suitable level for the NPN collectors. Unfortunately, it is impractical to provide the dose and energies needed to produce the "flat" N type epitaxial dopant concentration profile at the bottoms of the NPN collector regions. Consequently, the failure of the implanted ions to reach the bottoms of the NPN collector regions is a partial cause of the "dip" 20 in FIG. 2.
The problem of such light doping is further aggravated by boron autodoping, wherein a large number of P type boron atoms escape from the large P+ buried layer area and then diffuse into the surface of the P- substrate and into the lightly doped N type epitaxial layer being grown, reducing or "compensating" its dopant concentration. This results in increased collector resistance and corresponding increased V.sub.CE(sat) voltage, reduced f.sub.T (i.e., the unity gain frequency or cutoff frequency), lower NPN switching speeds, and higher power dissipation.
FIGS. 1 and 2 show typical dopant concentration profiles for the PNP and NPN collector regions, respectively, made by a conventional complementary bipolar process after completion of a field oxidation step, during which most of the dopant diffusion occurs.
The dopant profiles of FIGS. 1 and 2 were obtained from a simulation of the dopant diffusions for the conventional epitaxial deposition process. The process simulation was calibrated to match experimental results measured from a substrate with a large percentage (for example 80%) of the wafer surface area implanted with a dose of approximately 1.times.10.sup.15 cm.sup.-2 of boron followed by a P+ buried layer diffusion. (As those skilled in the art will recognize, the reason the large percentage of the P+ wafer substrate area has P+ "buried layer material" therein is to reduce substrate resistance and increase latch-up immunity of bipolar transistors and CMOS transistors.) The prior art epitaxial process referred to above includes a high temperature H.sub.2 pre-bake followed by a high temperature purge and then by a 1.5 micron deposition of an epitaxial layer of lightly arsenic (N type) doped single crystal silicon. The large amount of P+ surface area of the substrate causes a large amount of boron auto-doping into the lightly doped N type epitaxial layer being formed. The amount of corresponding boron P+ autodoping in the dopant concentration profile of prior art FIGS. 1 and 2 was computed using the TSUPREM-4. The simulated profiles were calibrated to match the measured experimental results. The TSUPREM-4 simulation program is a commercially available software package "Two-dimensional Process Simulation Program", sold by the TCAD division of Avant! Corporation, formerly Technology Modeling Associates.
For thin epitaxial layers (e.g., less than two microns in thickness), the autodoping strongly influences the transistor collector dopant concentration profiles. The large P+ substrate surface area mentioned above contributes a significant amount of boron autodoping during the epitaxial growth, which aggravates the above-mentioned problems with the performance of the NPN transistors, further reduces the depth of the PNP collector regions, and increases the difference between the breakdown characteristics of NPN and PNP transistors. The standard flat dopant profile epitaxial process techniques used to generate the profiles in prior art FIGS. 1 and 2 are not able to correct these problems.
Referring to FIGS. 1 and 2, the dopant concentration profiles of the prior art NPN and PNP collector regions are noticeably different when a standard epitaxial process is used. The differences between the depth of the peak of implant concentration (commonly referred to as Rp) for phosphorus and boron implants is another cause of the large difference in the dopant concentration profiles of the NPN and PNP collector regions when practical implant energies are used. This difference is further aggravated by the boron autodoping. The NPN collector region, doped by a combination of low and high energy implants, shows a significant dopant concentration dip at its bottom, indicated by reference arrows 20 in FIG. 2. This very lightly doped region adversely affects both the AC and DC performance of the NPN transistor by raising its collector region resistivity. This increases its collector resistance and thereby reduces f.sub.T and increases the collector-to-emitter saturation voltages of the NPN transistor.
Prior experimentation in forming arsenic doped N+ epitaxial caps in the hope of increasing the doping concentration at the bottoms of the NPN collector regions has failed to adequately compensate for the boron autodoping at the epitaxial/substrate interface.
Recently, single-wafer reactors in which a single semiconductor wafer is processed have been used, instead of using batch reactors in which a large number of semiconductor wafers are processed. Single wafer reactors provide much better reproducibility of complex dopant profiles in the wafer being processed than can be achieved with batch reactors, and also provide much better control over doping profiles of epitaxial layers than can be achieved with batch reactors. This is because single-wafer reactors have much chamber less interior surface area which can absorb the dopant and it is much easier and faster to remove dopant absorbed by smaller interior surface area. Single-wafer reactors also provide a much more rapid temperature stabilization than batch reactors. Single-wafer reactors have much less volume to pump down than batch reactors. The volume of a single-water reactor can be flushed much more rapidly than the volume of a batch reactor. Single-wafer reactors therefore have become widely used in the manufacture of extremely-thin epitaxial layers.
However, single-wafer reactor epi deposition cycles do not provide enough time at high temperature (i.e., do not provide enough Dt) to anneal out surface defects at the surface of the buried layer of the wafer being processed. These defects are the result of P+ buried layer implant operations and subsequent diffusions thereof.(Surface defects caused by formation of N+ buried layers are typically oxidized in sacrificial oxidation steps to consume the implant-caused defects. However, this approach can not work to consume surface defects caused by formation of P+ buried layers. That is because the P+ boron-implanted layers cannot be immediately oxidized after the implantation, since such oxidation would cause oxidation induced stacking faults (OISF).)
Another problem with use of single-wafer reactors is that it is not practical to perform slow rate temperature ramp-up procedures to heat a single wafer up to a high temperature, even though it is in fact practical and often unavoidable to perform slow rate temperature ramp-up procedures to heat up a large number of wafers in a batch reactor. Unfortunately, the fast temperature ramp-up procedures that are necessary to achieve an economically desired throughput for single-wafer reactors can not anneal out defects which are present in the semiconductor wafer. These defects would greatly reduce the yield of functional integrated circuits formed on the semiconductor wafer.
Thus, there is a need for an improved epitaxial process for complementary bipolar/CMOS for providing bipolar transistors, especially NPN transistors, with more ideal collector profiles leading to lower collector resistances and higher values of f.sub.T than has been previously achievable, and for providing such an epitaxial process in a single-wafer reactor without leaving a high density of crystal defects in integrated circuits.